Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC. Nevertheless, there are many factors that make the continued miniaturization of ICs difficult. For example, as the size of vias (or pathways between integrated circuit layers used to electrically connect separate conductive layers) decreases, electrical resistance increases.
Conventional integrated circuits utilize vias to connect structures (e.g., gates, drain regions, source regions) and conductive lines. For example, a via can connect a gate above the substrate to a conductor line in a metal 1 layer. Vias can also interconnect conductive lines. For example, a via can connect a conductive line in a metal 1 layer to a conductor line in a metal 2 layer. A via is typically a metal plug which extends through an insulative layer in a multilayer integrated circuit. Vias and barrier layers are discussed in U.S. Pat. Nos. 5,646,448; 5,770,519; and 5,639,691; each of which are assigned to the assignee of the present application.
A barrier layer is used to protect the via and insulative layer from metal diffusion and the via and conductive line from electromigration (EM). The barrier layer can contribute significantly to resistance associated with the via metal. Electromigration is the mass transport due to momentum exchange between conducting electrons and diffusing metal atoms. Electromigration causes progressive damage to the metal conductors in an integrated circuit. In general, metals are most susceptible to electromigration at very high current density and temperatures of 100° C. or more.
According to a conventional plasma vapor deposition (PVD) process, IC manufacturers deposit a very thin barrier layer of Tungsten (W). The barrier layer can be deposited in a SiH4, WFl6→WSi2 process. The barrier layer servers to adhere to the underlying dielectric layer and serve as a nucleation layer to further Tungsten deposition. Additional layers of Tungsten can be deposited in a WFI6+H2 deposition process without the use of SiH4.
Other conventional conductive lines have utilized pure copper or copper alloy lines formed in a damascene process. According to a conventional damascene process, copper lines are filled by electroplating a trench in a dielectric layer. The dielectric layer is typically covered by a barrier and/or a seed layer before electroplating to fill the trench with copper. After the trench is filled with copper, a barrier layer is provided above a copper conductive line and a subsequent interlevel dielectric layer is provided. The barrier layer is necessary to prevent electromigration and to protect the dielectric layer from copper diffusion. Further, the barrier layer reduces problems associated with having the dielectric material adhere to dielectric material.
Forming continuous barrier layers in ultra-narrow vias and metal lines can be difficult. Vias and trenches for the metal lines can be less than 160 nm in width, making formation of continuous and conformal barrier and/or seed layers challenging. As IC fabrication techniques improve, the via and trench widths become ever smaller. Therefore, metallization of in-laid trenches and vias is becoming a more difficult task.
Thus, there is a need for method of using an adhesion precursor for chemical vapor deposition (CVD) copper deposition. Further, there is a need for a method of causing copper to better adhere to dielectric material to form a continuous barrier layer in vias and metal lines. Even further, there is a need for an improved electromigration barrier.